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Electricity & Electrons

PCB Signal Integrity: Impedance, Differential Pairs, and Return Paths

When a Trace Becomes a Transmission Line

PCB signal integrity diagram showing controlled impedance traces, differential pairs, the return current path on the reference plane under the trace, reflections and crosstalk

Imagine you designed a board running at 1MHz and it worked perfectly. You raise the clock to 500MHz and suddenly the signal distorts and random errors appear. The copper trace never changed — but its behavior did. This is the core of signal integrity: the study of how a fast or digital signal keeps its shape and timing as it travels across PCB traces. At high speed a trace stops being a simple "wire" and becomes a transmission line with a characteristic impedance, a return path, and a propagation delay.

The deciding factor is not frequency alone but rise time — how fast the edge moves from low to high. Sharp edges contain high-frequency content even when the base clock is slow.

The Practical Rule: "Electrically Long"

A signal travels through copper at roughly 15cm/ns (about half the speed of light, slowed by the board dielectric). Compare the trace length to the distance the edge covers during its rise time:

  • If the trace is shorter than about 1/6 of the "rise-time distance" → treat it as an ordinary wire.
  • If it is longer → it is electrically long and transmission-line rules apply.

Example: a 1ns rise time covers about 15cm; one sixth is ≈ 2.5cm. Any trace longer than that can generate reflections. Your DC intuition fails completely here.

Controlled Impedance

Once a trace is a transmission line it has a property called characteristic impedance Z0 — not an ohmic resistance, but the voltage-to-current ratio of the travelling wave. The goal is to keep Z0 constant along the trace and matched to source and load.

Common standard targets:

Application Signal type Target impedance
General single-ended traces single-ended 50Ω
USB 2.0 differential 90Ω
Ethernet / LVDS / HDMI differential 100Ω

What Sets Z0?

Three factors in the stackup control impedance:

  1. Trace width — wider trace lowers Z0.
  2. Dielectric height above the reference plane — closer to the plane lowers Z0.
  3. Dielectric constant Dk of the material (about 4.2 for FR-4).
Structure Location Reference plane
microstrip on an outer layer one ground plane beneath it
stripline buried between layers two planes surrounding it

Ask your fab for an impedance-control service and hand them the required stackup; they will tune the trace widths to about ±10% instead of you guessing them.

Differential Pairs

In a differential pair the signal is sent on two adjacent traces carrying opposite voltages, and the receiver reads the difference between them. This is the basis of USB, Ethernet, HDMI, and LVDS.

The key benefit is noise rejection: any interference picked up by both traces equally (common-mode noise) is subtracted at the receiver and disappears.

To achieve this you must:

  • Tight coupling: keep the two traces close, at a constant spacing, along the entire route.
  • Route together: run them side by side, never letting them split around obstacles.
  • Maintain constant spacing so the differential impedance (90Ω/100Ω) holds.

Length Matching and Skew

If the two traces of a pair differ in length, one edge arrives before the other, creating skew that breaks the symmetry of the differential signal. Likewise, in a parallel bus every bit must arrive at the same instant.

Two kinds of matching:

Type What we match Tool
Intra-pair the two traces inside one pair short serpentines near the mismatch
Parallel bus several data traces plus the clock length tuning with serpentine meanders

Matching is not always required: it becomes critical only when skew approaches the timing budget. For a slow signal, do not bother with elaborate meanders.

Route first, then measure the length difference, then add serpentine meanders to the shorter trace to equalize it. Finish the matching near the source of the mismatch, not at the far end.

Return Path and Reference Plane

This is the single most common mistake designers make. Every current needs a return path. At low frequency the return takes the shortest copper route, but at high frequency the return current flows in the reference plane directly under the trace, because that path has the lowest inductance.

Practical consequences:

  • Never cross a plane split: if the copper under the trace is interrupted, the return current is forced to detour, inductance rises, and you get EMI and a distorted signal.
  • On a layer change: place a return via for ground next to the signal via so the current can reach the new plane.
  • Always keep a continuous, clean reference plane beneath fast traces.

Golden rule: "the signal never travels alone — its return travels with it." Ignore the return path and you have designed an antenna that radiates noise.

Termination and Reflections

When the wave reaches a point whose impedance differs from Z0 (an unmatched source or load), part of it reflects back. Reflections show up as ringing, overshoot, and false levels that may be read as wrong bits.

The cure is termination — matching the impedance at an end:

Type Location How it works
Series at the source a resistor that completes the driver impedance to equal Z0
Parallel at the load a resistor to a reference that absorbs the wave at Z0

When do you terminate? When the trace is electrically long and its edges are sharp. Short or slow traces may need no termination at all. Series termination is common for point-to-point links because it draws no DC current.

Crosstalk Between Traces

Crosstalk is signal leaking from an "aggressor" trace into a "victim" trace through capacitive and inductive coupling between them. The closer and the longer the two run parallel, the worse the crosstalk.

Ways to reduce it:

  1. The 3W rule: keep the spacing between trace centers at least three times the trace width W to cut coupling sharply.
  2. Ground guard traces: place a via-stitched ground trace between aggressor and victim.
  3. Separate aggressors from victims: keep fast, sharp-edged traces away from sensitive analog nets.
  4. Keep clocks away: clock traces are among the strongest aggressors; route them far from any sensitive net and never run them parallel for long.

Also shorten the parallel run: a short brush of crosstalk over a few millimeters is far gentler than a side-by-side run of several centimeters.

Summary

Signal integrity is not magic — it is transmission-line physics applied to copper. For the practical designer, order your priorities like this:

  • Know the rise time: it decides whether a trace is "electrically long" and needs special treatment.
  • Control impedance (50Ω single-ended, 90/100Ω differential) through the stackup and the fab's impedance-control service.
  • Route differential pairs together with tight coupling and constant spacing; match lengths only when skew demands it.
  • Protect the return path: never cross plane splits, and add return vias on layer changes — this is the mistake to avoid.
  • Terminate long traces to kill reflections, and space traces with the 3W rule plus guard traces to limit crosstalk.

Follow these five rules and your board will work the first time, instead of chasing ghosts in the signal later.

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